1. Technical Field
The present invention relates to an improvement in LSI (large-scale integrated circuit) automatic design technology for automating top-down design processing from the design of LSI functions to the design of LSI mask layouts.
2. Technical Background
In recent years the market life of electronic apparatus that employ LSIs has been reduced and their performance has been improved. There have been demands in the field of design automation (DA) technology for (1) reduction of the design time and (2) high-quality design (high performance).
Prior art DA techniques, however, have the following problems.
(A) Tool processes at different design stages are independently performed, which makes it impossible to adequately perform upper-stage processing while taking into account lower-stage processing (for example, a layout design process), in other words no optimum processing can be achieved.
(B) It is difficult to exactly predict, at a tool process of one design stage, another tool process of the other design stage. This results in producing the difference between (a) a wiring delay that is assumed in an upper-stage logic design process and (b) a wiring delay from a layout result obtained in a lower-stage layout design process. Accordingly, in some cases the wiring delay (b) may exceed the wiring delay (a).
As a solution to these problems, a technique known as "timing driven" has been proposed recently. In accordance with this timing driven technique, upper-stage processing and lower-stage processing are related with each other and constraints, which satisfy a delay assumed in an upper-stage logic design process, are placed on an upper-stage layout design process, in order to cope with the drawbacks (A) and (B).
Additionally, placement techniques, which take in account a delay between registers, have been developed in the layout design from logic gate level, to obtain results that satisfy timing constraints.
However, in conventional techniques, timing constraints are placed one-sidedly from an upper-stage logic design process under no physical constraints, onto a lower-stage layout design process under physical constraints. Accordingly, in some cases it may become impossible, due to various other layout constraints such as placement positions and wiring relations, to produce a layout result that satisfies a timing constraint. In such a case, it is necessary to make a change in the circuit configuration. It is therefore required to redo a circuit synthesis process over again and thereafter to find a layout result that satisfies the constraints of timing. However, both the circuit synthesis and the layout design are a time-consuming process. It takes, for example, about one week to finish such processing. This not only prolongs the LSI development period but also increases the LSI production cost.
To be immune from the foregoing problems, it can be thought of setting a wiring delay, assumed in a logic design process, to such an extent that the wiring delay can be realized even in the worst case. However, it is necessary to prepare a great number of output transistors and a faster circuit structure is required. As a result, the scale of circuit increases, therefore presenting the problem that the cost of LSI products increases.
Such problems occur to both clock wiring and scan path wiring. It is impossible to predict the post-layout position of clock input elements such as registers in a logic design process. This increases the length of clock wiring, inevitably leading to an increase in the power consumption, to the occurrence of malfunctions due to clock skew and to an increase in the wiring area. Additionally, an increase in the wiring area due to scan path wiring occurs for the same reason.
The root of the problem in question may be circumvented by taking into account a laying-out at the time of a logic design process. It is, however, difficult to determine a circuit-scale specification or a delay-value specification in an upper-stage functional design process and it is therefore difficult to become aware of a lower-stage layout in an upper-stage functional design process. For this reason, conventionally a laying-out is considered at, for example, the stage of gate level. In such a case, however, a laying-out is considered at the gate level stage (the lower stage), so that it is hard to make a great change in the circuit area as well as in the delay value. Accordingly, it is necessary to repeat a circuit synthesis process over again and the foregoing problem cannot be solved basically.